Intel810 Chipset

Intel810 System Architecture
Intel810 chipset (Whitney) introduces a new architecture in comparison to the previous ones such as 440BX, 440LX, etc. The Intel810 is the first in a series of Intel chipset products that are based on the Accelerated Hub Architecture, which removes the PCI bus as the main device interconnection. The major changes include:

1. GMCH (Graphics & Memory Controller Hub) is used as the North Bridge, and ICH (I/O Controller Hub) as the South Bridge.
2. Hub Interface interconnects GMCH and ICH.
3. Graphics Engine is built into the GMCH and shares system memory for display purpose.
4. AC'97 is the default configuration of audio and modem.
5. LPC (Low Pin Count) Interface replaces ISA and is used for connection of legacy ISA & X-Bus devices.
6. FWH (Firmware Hub) contains non-volatile memory for BIOS codes and a hardware random number generator.

The block diagram of Intel810 is illustrated in Figure 1.

Figure 1. Intel810 System Architecture

As indicated in the Figure 1, PCI is no longer the interconnection between GMCH and ICH. Instead, a high-speed (clocked at 66MHz), narrow (8-bit wide) and dedicated interface named Hub Interface is used. Hub interface transfers up to 266MB/sec.

GMCH
The GMCH is composed of

1. A graphics engine with analog and digital outputs.
2. A memory controller for both system memory and display cache (for 82810-DC100 only), and
3. Control logic circuits for system bus interface (from/to CPU) and hub interface (from/to ICH).

The DVM (Dynamic Video Memory) technology is used for the on-chip graphics engine to dynamically share a portion of system memory for display purpose. This means that the system will change the allocation of the display memory accordingly in order to prevent waste of memory resources. For 82810-DC100 chip, display cache could be connected for storage of Z-buffer during 3D rendering. This alleviates the occupation of system memory and enhances 3D graphics performance. Display cache interface is a 32-bit wide SDRAM interface clocked at 100MHz. Note that no AGP interface comes out from the GMCH because of the built-in graphics engine.

ICH
ICH supports functions that were originally provided by PIIX4 except the following:

1. LPC interface is used for connection of legacy ISA and X-Bus devices to enable a system that has no ISA or X-Bus.
2. AC'97 is the default configuration of audio and modem.

LPC interface is a 4-bit wide multiplexed command, address, and data bus, which is clocked at 33MHz. The number of the required pins is only 7, hence the "Low Pin Count" name. Because the Intel810 chipset doesn't provide the ISA interface, ISA bridge chip is necessary if ISA expansions are needed. AC'97 stands for Audio Codec '97, which is a two-chip configuration for audio or modem. In AC'97 configuration, digital signal processing and conversion between analog and digital circuitry does not reside on the same chip. Instead, there is one chip for digital signal processing and another for analog and digital conversion. A higher SNR (signal to noise ratio) can be expected after the separation.

FWH
FWH is where BIOS code resides in an Intel810 system. In addition, one hardware random number generator is available for truly random number generation. It uses white noise on the chip as the random source to avoid a predictable seed and also to eliminate the possibility for a cycled sequence. The applications of random number generation include electronic commerce, digital signature, protected communication protocol, and entertainment.